A chiplet[1][2][3][4] is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC):

  • Reusable IP (intellectual property):[5] the same chiplet can be used in many different devices
  • Heterogeneous integration:[6] chiplets can be fabricated with different processes, materials, and nodes, each optimized for its particular function
  • Known good die:[7] chiplets can be tested before assembly, improving the yield of the final device

Multiple chiplets working together in a single integrated circuit may be called a multi-chip module, hybrid IC, 2.5D IC, or an advanced package.

Chiplets may be connected with standards such as UCIe, bunch of wires (BoW), OpenHBI, and OIF XSR.

The term was coined by University of California, Berkeley professor John Wawrzynek as a component of the RAMP Project (research accelerator for multiple processors) in 2006 [8][9] extension for the Department of Energy, as was RISC-V architecture.

Common examples include:

See also

References

  1. ↑ Brookes (25 July 2021). "What Is a Chiplet?". How-To Geek. Retrieved 28 December 2021.
  2. ↑ "Chiplet". WikiChip. Retrieved 28 December 2021.
  3. ↑ Semi Engineering "Chiplets" Retrieved 5 December 2022
  4. ↑ Don Scansen, EE Times "Chiplets: A Short History Retrieved 5 December 2022
  5. ↑ Keeler. "Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)". DARPA. Retrieved 28 December 2021.
  6. ↑ Kenyon (6 April 2021). "Heterogeneous Integration and the Evolution of IC Packaging". EE Times Europe. Retrieved 28 December 2021.
  7. ↑ Bertin, Claude L.; Su, Lo-Soun; Van Horn, Jody (2001). "Known Good die (KGD)". Area Array Interconnection Handbook. SpringerLink. pp. 149–200. doi:10.1007/978-1-4615-1389-6_4. ISBN 978-1-4613-5529-8. Retrieved 7 October 2022.
  8. ↑ Patterson, D.A. (March 2006). "RAMP: Research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform". 2006 IEEE International Symposium on Performance Analysis of Systems and Software. pp. 1–. doi:10.1109/ISPASS.2006.1620784. ISBN 1-4244-0186-0.
  9. ↑ Wawrzynek, John (2015-05-01). "Accelerating Science Driven System Design With RAMP". UCB. OSTI 1186854.

Further reading

This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.