Computer architecture

Conte realized in the early 1990s that Flynn's prediction of the fetch bandwidth being the limit to increasing instruction-level parallelism was coming true. His oft-cited International Symposium on Computer Architecture paper and subsequent work on instruction fetch mechanisms have influenced industry and spawned much follow-on research. More recently, Conte and his Ph.D. students invented a technique to predict data values with very high (~90%) accuracy and showed how predicting data values can be used to scale the memory wall by enabling aggressive prefetching. The work is of great interest to industry design teams who are struggling with performance limitations imposed by the speed gap between microprocessors and memory systems. Conte and his students have also developed a very small yet highly effective prefetcher termed the Spectral Prefetcher. This was published in the ACM Transactions on Computer Systems.

Conte has also contributed to EPIC architectures. One well-known example is that his technique for the then-pressing problem (ca. early ‘90s) of VLIW cross-generation code compatibility. In a technique he and his students termed “dynamic rescheduling,” Conte brought to bear on the problem collaboration between the ISA, the hardware and the compiler to reschedule code with minimal performance loss at first-time page misses to the code. This work has major implications on the long-term viability of the EPIC architecture proposed in Intel Itanium processor family. The research also helped make code optimization during runtime a practical approach. In this way, his research is now also considered one of the pioneering works on dynamic code optimization. One of his Ph.D. students went on to build tools such as the HP Dynamo dynamic optimizer and another Ph.D. student went on to build the IBM DAISY dynamic optimizer.

Compiler code generation

Conte has also made significant contributions to profile-driven optimization. He was the first to realize that the limit to profile-driven optimization wasn't the technology itself, but it was the slowdown due to profiling that prevented its adoption by industry. He and his students devised clever techniques to extract profile information from branch predictors on Intel Pentium processor. He then went on to prescribe new design criteria for microprocessor performance monitoring hardware to make such hardware useful to a compiler. The results are reflected in the performance counters that are present in the Intel Itanium, co-designed by one of Conte's Ph.D. students (Kishore Menezes). In compiler code generation, Conte developed Treegion Scheduling, a novel technique for code scheduling that is used today in VLIW DSP compilers. The technique can produce performance similar to Scott Mahlke's hyperblock scheduling, but without needing predication support in the hardware. He and his students also invented a technique for scheduling code in the presence of distributed register files (as are common in DSPs), optimizing code for both run time efficiency and code size efficiency (as is critical for embedded code), and exploiting value locality in code generation of EPIC architectures.

Computer performance analysis

Conte has devised long lasting and important techniques for fast simulation of computer architectures. One example of this are his techniques for applying sampling to processor performance studies in such a way as to allow the calculation of confidence intervals. Prior to that work, there had been no attempt to introduce error bar calculations into sampling. The results were expected to be taken on faith alone. He similarly pioneered fast simulation techniques for caches and processor pipelines. He continues to be active here and has consulted on this topic for many companies, including AT&T, IBM, NCR S3 (SONICblue) and Qualcomm.

Rebooting Computing

In late 2012, Conte along with Elie Track proposed the IEEE Rebooting Computing Initiative.^[7] This initiative has had major influence on US and international research priorities .