In integrated circuit design, VerilogCSP [1] is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

References

  1. ↑ Saifhashemi, Arash; Peter Beerel (2005). "High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog". In Jan Broenink; Herman Roebbers; Johan Sunter; Peter Welch; David Wood (eds.). Communicating Process Architectures 2005. IOS Press. p. 275.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.